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Open Menu / tools / perf / pmu-events / arch / arm64 / hisilicon / hip08 / core-imp-def.json
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[
    {
        "ArchStdEvent": "L1D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L1D_CACHE_INVAL"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_TLB_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L2D_CACHE_INVAL"
    },
    {
        "PublicDescription": "Level 1 instruction cache prefetch access count",
        "EventCode": "0x102e",
        "EventName": "L1I_CACHE_PRF",
        "BriefDescription": "L1I cache prefetch access count"
    },
    {
        "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
        "EventCode": "0x102f",
        "EventName": "L1I_CACHE_PRF_REFILL",
        "BriefDescription": "L1I cache miss due to prefetch access count"
    },
    {
        "PublicDescription": "Instruction queue is empty",
        "EventCode": "0x1043",
        "EventName": "IQ_IS_EMPTY",
        "BriefDescription": "Instruction queue is empty"
    },
    {
        "PublicDescription": "Instruction fetch stall cycles",
        "EventCode": "0x1044",
        "EventName": "IF_IS_STALL",
        "BriefDescription": "Instruction fetch stall cycles"
    },
    {
        "PublicDescription": "Instructions can receive, but not send",
        "EventCode": "0x2014",
        "EventName": "FETCH_BUBBLE",
        "BriefDescription": "Instructions can receive, but not send"
    },
    {
        "PublicDescription": "Prefetch request from LSU",
        "EventCode": "0x6013",
        "EventName": "PRF_REQ",
        "BriefDescription": "Prefetch request from LSU"
    },
    {
        "PublicDescription": "Hit on prefetched data",
        "EventCode": "0x6014",
        "EventName": "HIT_ON_PRF",
        "BriefDescription": "Hit on prefetched data"
    },
    {
        "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
        "EventCode": "0x7001",
        "EventName": "EXE_STALL_CYCLE",
        "BriefDescription": "Cycles of that the number of issue ups are less than 4"
    },
    {
        "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
        "EventCode": "0x7004",
        "EventName": "MEM_STALL_ANYLOAD",
        "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved"
    },
    {
        "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
        "EventCode": "0x7006",
        "EventName": "MEM_STALL_L1MISS",
        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill"
    },
    {
        "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
        "EventCode": "0x7007",
        "EventName": "MEM_STALL_L2MISS",
        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache"
    }
]