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/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_NIC3_QM1_REGS_H_ #define ASIC_REG_NIC3_QM1_REGS_H_ /* ***************************************** * NIC3_QM1 (Prototype: QMAN) ***************************************** */ #define mmNIC3_QM1_GLBL_CFG0 0xDA2000 #define mmNIC3_QM1_GLBL_CFG1 0xDA2004 #define mmNIC3_QM1_GLBL_PROT 0xDA2008 #define mmNIC3_QM1_GLBL_ERR_CFG 0xDA200C #define mmNIC3_QM1_GLBL_SECURE_PROPS_0 0xDA2010 #define mmNIC3_QM1_GLBL_SECURE_PROPS_1 0xDA2014 #define mmNIC3_QM1_GLBL_SECURE_PROPS_2 0xDA2018 #define mmNIC3_QM1_GLBL_SECURE_PROPS_3 0xDA201C #define mmNIC3_QM1_GLBL_SECURE_PROPS_4 0xDA2020 #define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0 0xDA2024 #define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1 0xDA2028 #define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2 0xDA202C #define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3 0xDA2030 #define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4 0xDA2034 #define mmNIC3_QM1_GLBL_STS0 0xDA2038 #define mmNIC3_QM1_GLBL_STS1_0 0xDA2040 #define mmNIC3_QM1_GLBL_STS1_1 0xDA2044 #define mmNIC3_QM1_GLBL_STS1_2 0xDA2048 #define mmNIC3_QM1_GLBL_STS1_3 0xDA204C #define mmNIC3_QM1_GLBL_STS1_4 0xDA2050 #define mmNIC3_QM1_GLBL_MSG_EN_0 0xDA2054 #define mmNIC3_QM1_GLBL_MSG_EN_1 0xDA2058 #define mmNIC3_QM1_GLBL_MSG_EN_2 0xDA205C #define mmNIC3_QM1_GLBL_MSG_EN_3 0xDA2060 #define mmNIC3_QM1_GLBL_MSG_EN_4 0xDA2068 #define mmNIC3_QM1_PQ_BASE_LO_0 0xDA2070 #define mmNIC3_QM1_PQ_BASE_LO_1 0xDA2074 #define mmNIC3_QM1_PQ_BASE_LO_2 0xDA2078 #define mmNIC3_QM1_PQ_BASE_LO_3 0xDA207C #define mmNIC3_QM1_PQ_BASE_HI_0 0xDA2080 #define mmNIC3_QM1_PQ_BASE_HI_1 0xDA2084 #define mmNIC3_QM1_PQ_BASE_HI_2 0xDA2088 #define mmNIC3_QM1_PQ_BASE_HI_3 0xDA208C #define mmNIC3_QM1_PQ_SIZE_0 0xDA2090 #define mmNIC3_QM1_PQ_SIZE_1 0xDA2094 #define mmNIC3_QM1_PQ_SIZE_2 0xDA2098 #define mmNIC3_QM1_PQ_SIZE_3 0xDA209C #define mmNIC3_QM1_PQ_PI_0 0xDA20A0 #define mmNIC3_QM1_PQ_PI_1 0xDA20A4 #define mmNIC3_QM1_PQ_PI_2 0xDA20A8 #define mmNIC3_QM1_PQ_PI_3 0xDA20AC #define mmNIC3_QM1_PQ_CI_0 0xDA20B0 #define mmNIC3_QM1_PQ_CI_1 0xDA20B4 #define mmNIC3_QM1_PQ_CI_2 0xDA20B8 #define mmNIC3_QM1_PQ_CI_3 0xDA20BC #define mmNIC3_QM1_PQ_CFG0_0 0xDA20C0 #define mmNIC3_QM1_PQ_CFG0_1 0xDA20C4 #define mmNIC3_QM1_PQ_CFG0_2 0xDA20C8 #define mmNIC3_QM1_PQ_CFG0_3 0xDA20CC #define mmNIC3_QM1_PQ_CFG1_0 0xDA20D0 #define mmNIC3_QM1_PQ_CFG1_1 0xDA20D4 #define mmNIC3_QM1_PQ_CFG1_2 0xDA20D8 #define mmNIC3_QM1_PQ_CFG1_3 0xDA20DC #define mmNIC3_QM1_PQ_ARUSER_31_11_0 0xDA20E0 #define mmNIC3_QM1_PQ_ARUSER_31_11_1 0xDA20E4 #define mmNIC3_QM1_PQ_ARUSER_31_11_2 0xDA20E8 #define mmNIC3_QM1_PQ_ARUSER_31_11_3 0xDA20EC #define mmNIC3_QM1_PQ_STS0_0 0xDA20F0 #define mmNIC3_QM1_PQ_STS0_1 0xDA20F4 #define mmNIC3_QM1_PQ_STS0_2 0xDA20F8 #define mmNIC3_QM1_PQ_STS0_3 0xDA20FC #define mmNIC3_QM1_PQ_STS1_0 0xDA2100 #define mmNIC3_QM1_PQ_STS1_1 0xDA2104 #define mmNIC3_QM1_PQ_STS1_2 0xDA2108 #define mmNIC3_QM1_PQ_STS1_3 0xDA210C #define mmNIC3_QM1_CQ_CFG0_0 0xDA2110 #define mmNIC3_QM1_CQ_CFG0_1 0xDA2114 #define mmNIC3_QM1_CQ_CFG0_2 0xDA2118 #define mmNIC3_QM1_CQ_CFG0_3 0xDA211C #define mmNIC3_QM1_CQ_CFG0_4 0xDA2120 #define mmNIC3_QM1_CQ_CFG1_0 0xDA2124 #define mmNIC3_QM1_CQ_CFG1_1 0xDA2128 #define mmNIC3_QM1_CQ_CFG1_2 0xDA212C #define mmNIC3_QM1_CQ_CFG1_3 0xDA2130 #define mmNIC3_QM1_CQ_CFG1_4 0xDA2134 #define mmNIC3_QM1_CQ_ARUSER_31_11_0 0xDA2138 #define mmNIC3_QM1_CQ_ARUSER_31_11_1 0xDA213C #define mmNIC3_QM1_CQ_ARUSER_31_11_2 0xDA2140 #define mmNIC3_QM1_CQ_ARUSER_31_11_3 0xDA2144 #define mmNIC3_QM1_CQ_ARUSER_31_11_4 0xDA2148 #define mmNIC3_QM1_CQ_STS0_0 0xDA214C #define mmNIC3_QM1_CQ_STS0_1 0xDA2150 #define mmNIC3_QM1_CQ_STS0_2 0xDA2154 #define mmNIC3_QM1_CQ_STS0_3 0xDA2158 #define mmNIC3_QM1_CQ_STS0_4 0xDA215C #define mmNIC3_QM1_CQ_STS1_0 0xDA2160 #define mmNIC3_QM1_CQ_STS1_1 0xDA2164 #define mmNIC3_QM1_CQ_STS1_2 0xDA2168 #define mmNIC3_QM1_CQ_STS1_3 0xDA216C #define mmNIC3_QM1_CQ_STS1_4 0xDA2170 #define mmNIC3_QM1_CQ_PTR_LO_0 0xDA2174 #define mmNIC3_QM1_CQ_PTR_HI_0 0xDA2178 #define mmNIC3_QM1_CQ_TSIZE_0 0xDA217C #define mmNIC3_QM1_CQ_CTL_0 0xDA2180 #define mmNIC3_QM1_CQ_PTR_LO_1 0xDA2184 #define mmNIC3_QM1_CQ_PTR_HI_1 0xDA2188 #define mmNIC3_QM1_CQ_TSIZE_1 0xDA218C #define mmNIC3_QM1_CQ_CTL_1 0xDA2190 #define mmNIC3_QM1_CQ_PTR_LO_2 0xDA2194 #define mmNIC3_QM1_CQ_PTR_HI_2 0xDA2198 #define mmNIC3_QM1_CQ_TSIZE_2 0xDA219C #define mmNIC3_QM1_CQ_CTL_2 0xDA21A0 #define mmNIC3_QM1_CQ_PTR_LO_3 0xDA21A4 #define mmNIC3_QM1_CQ_PTR_HI_3 0xDA21A8 #define mmNIC3_QM1_CQ_TSIZE_3 0xDA21AC #define mmNIC3_QM1_CQ_CTL_3 0xDA21B0 #define mmNIC3_QM1_CQ_PTR_LO_4 0xDA21B4 #define mmNIC3_QM1_CQ_PTR_HI_4 0xDA21B8 #define mmNIC3_QM1_CQ_TSIZE_4 0xDA21BC #define mmNIC3_QM1_CQ_CTL_4 0xDA21C0 #define mmNIC3_QM1_CQ_PTR_LO_STS_0 0xDA21C4 #define mmNIC3_QM1_CQ_PTR_LO_STS_1 0xDA21C8 #define mmNIC3_QM1_CQ_PTR_LO_STS_2 0xDA21CC #define mmNIC3_QM1_CQ_PTR_LO_STS_3 0xDA21D0 #define mmNIC3_QM1_CQ_PTR_LO_STS_4 0xDA21D4 #define mmNIC3_QM1_CQ_PTR_HI_STS_0 0xDA21D8 #define mmNIC3_QM1_CQ_PTR_HI_STS_1 0xDA21DC #define mmNIC3_QM1_CQ_PTR_HI_STS_2 0xDA21E0 #define mmNIC3_QM1_CQ_PTR_HI_STS_3 0xDA21E4 #define mmNIC3_QM1_CQ_PTR_HI_STS_4 0xDA21E8 #define mmNIC3_QM1_CQ_TSIZE_STS_0 0xDA21EC #define mmNIC3_QM1_CQ_TSIZE_STS_1 0xDA21F0 #define mmNIC3_QM1_CQ_TSIZE_STS_2 0xDA21F4 #define mmNIC3_QM1_CQ_TSIZE_STS_3 0xDA21F8 #define mmNIC3_QM1_CQ_TSIZE_STS_4 0xDA21FC #define mmNIC3_QM1_CQ_CTL_STS_0 0xDA2200 #define mmNIC3_QM1_CQ_CTL_STS_1 0xDA2204 #define mmNIC3_QM1_CQ_CTL_STS_2 0xDA2208 #define mmNIC3_QM1_CQ_CTL_STS_3 0xDA220C #define mmNIC3_QM1_CQ_CTL_STS_4 0xDA2210 #define mmNIC3_QM1_CQ_IFIFO_CNT_0 0xDA2214 #define mmNIC3_QM1_CQ_IFIFO_CNT_1 0xDA2218 #define mmNIC3_QM1_CQ_IFIFO_CNT_2 0xDA221C #define mmNIC3_QM1_CQ_IFIFO_CNT_3 0xDA2220 #define mmNIC3_QM1_CQ_IFIFO_CNT_4 0xDA2224 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDA2228 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDA222C #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDA2230 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDA2234 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDA2238 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDA223C #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDA2240 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDA2244 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDA2248 #define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDA224C #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDA2250 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDA2254 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDA2258 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDA225C #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDA2260 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDA2264 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDA2268 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDA226C #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDA2270 #define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDA2274 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDA2278 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDA227C #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDA2280 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDA2284 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDA2288 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDA228C #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDA2290 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDA2294 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDA2298 #define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDA229C #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDA22A0 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDA22A4 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDA22A8 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDA22AC #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDA22B0 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDA22B4 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDA22B8 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDA22BC #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDA22C0 #define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDA22C4 #define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDA22C8 #define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDA22CC #define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDA22D0 #define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDA22D4 #define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDA22D8 #define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA22E0 #define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA22E4 #define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA22E8 #define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA22EC #define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA22F0 #define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA22F4 #define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA22F8 #define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA22FC #define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA2300 #define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA2304 #define mmNIC3_QM1_CP_FENCE0_RDATA_0 0xDA2308 #define mmNIC3_QM1_CP_FENCE0_RDATA_1 0xDA230C #define mmNIC3_QM1_CP_FENCE0_RDATA_2 0xDA2310 #define mmNIC3_QM1_CP_FENCE0_RDATA_3 0xDA2314 #define mmNIC3_QM1_CP_FENCE0_RDATA_4 0xDA2318 #define mmNIC3_QM1_CP_FENCE1_RDATA_0 0xDA231C #define mmNIC3_QM1_CP_FENCE1_RDATA_1 0xDA2320 #define mmNIC3_QM1_CP_FENCE1_RDATA_2 0xDA2324 #define mmNIC3_QM1_CP_FENCE1_RDATA_3 0xDA2328 #define mmNIC3_QM1_CP_FENCE1_RDATA_4 0xDA232C #define mmNIC3_QM1_CP_FENCE2_RDATA_0 0xDA2330 #define mmNIC3_QM1_CP_FENCE2_RDATA_1 0xDA2334 #define mmNIC3_QM1_CP_FENCE2_RDATA_2 0xDA2338 #define mmNIC3_QM1_CP_FENCE2_RDATA_3 0xDA233C #define mmNIC3_QM1_CP_FENCE2_RDATA_4 0xDA2340 #define mmNIC3_QM1_CP_FENCE3_RDATA_0 0xDA2344 #define mmNIC3_QM1_CP_FENCE3_RDATA_1 0xDA2348 #define mmNIC3_QM1_CP_FENCE3_RDATA_2 0xDA234C #define mmNIC3_QM1_CP_FENCE3_RDATA_3 0xDA2350 #define mmNIC3_QM1_CP_FENCE3_RDATA_4 0xDA2354 #define mmNIC3_QM1_CP_FENCE0_CNT_0 0xDA2358 #define mmNIC3_QM1_CP_FENCE0_CNT_1 0xDA235C #define mmNIC3_QM1_CP_FENCE0_CNT_2 0xDA2360 #define mmNIC3_QM1_CP_FENCE0_CNT_3 0xDA2364 #define mmNIC3_QM1_CP_FENCE0_CNT_4 0xDA2368 #define mmNIC3_QM1_CP_FENCE1_CNT_0 0xDA236C #define mmNIC3_QM1_CP_FENCE1_CNT_1 0xDA2370 #define mmNIC3_QM1_CP_FENCE1_CNT_2 0xDA2374 #define mmNIC3_QM1_CP_FENCE1_CNT_3 0xDA2378 #define mmNIC3_QM1_CP_FENCE1_CNT_4 0xDA237C #define mmNIC3_QM1_CP_FENCE2_CNT_0 0xDA2380 #define mmNIC3_QM1_CP_FENCE2_CNT_1 0xDA2384 #define mmNIC3_QM1_CP_FENCE2_CNT_2 0xDA2388 #define mmNIC3_QM1_CP_FENCE2_CNT_3 0xDA238C #define mmNIC3_QM1_CP_FENCE2_CNT_4 0xDA2390 #define mmNIC3_QM1_CP_FENCE3_CNT_0 0xDA2394 #define mmNIC3_QM1_CP_FENCE3_CNT_1 0xDA2398 #define mmNIC3_QM1_CP_FENCE3_CNT_2 0xDA239C #define mmNIC3_QM1_CP_FENCE3_CNT_3 0xDA23A0 #define mmNIC3_QM1_CP_FENCE3_CNT_4 0xDA23A4 #define mmNIC3_QM1_CP_STS_0 0xDA23A8 #define mmNIC3_QM1_CP_STS_1 0xDA23AC #define mmNIC3_QM1_CP_STS_2 0xDA23B0 #define mmNIC3_QM1_CP_STS_3 0xDA23B4 #define mmNIC3_QM1_CP_STS_4 0xDA23B8 #define mmNIC3_QM1_CP_CURRENT_INST_LO_0 0xDA23BC #define mmNIC3_QM1_CP_CURRENT_INST_LO_1 0xDA23C0 #define mmNIC3_QM1_CP_CURRENT_INST_LO_2 0xDA23C4 #define mmNIC3_QM1_CP_CURRENT_INST_LO_3 0xDA23C8 #define mmNIC3_QM1_CP_CURRENT_INST_LO_4 0xDA23CC #define mmNIC3_QM1_CP_CURRENT_INST_HI_0 0xDA23D0 #define mmNIC3_QM1_CP_CURRENT_INST_HI_1 0xDA23D4 #define mmNIC3_QM1_CP_CURRENT_INST_HI_2 0xDA23D8 #define mmNIC3_QM1_CP_CURRENT_INST_HI_3 0xDA23DC #define mmNIC3_QM1_CP_CURRENT_INST_HI_4 0xDA23E0 #define mmNIC3_QM1_CP_BARRIER_CFG_0 0xDA23F4 #define mmNIC3_QM1_CP_BARRIER_CFG_1 0xDA23F8 #define mmNIC3_QM1_CP_BARRIER_CFG_2 0xDA23FC #define mmNIC3_QM1_CP_BARRIER_CFG_3 0xDA2400 #define mmNIC3_QM1_CP_BARRIER_CFG_4 0xDA2404 #define mmNIC3_QM1_CP_DBG_0_0 0xDA2408 #define mmNIC3_QM1_CP_DBG_0_1 0xDA240C #define mmNIC3_QM1_CP_DBG_0_2 0xDA2410 #define mmNIC3_QM1_CP_DBG_0_3 0xDA2414 #define mmNIC3_QM1_CP_DBG_0_4 0xDA2418 #define mmNIC3_QM1_CP_ARUSER_31_11_0 0xDA241C #define mmNIC3_QM1_CP_ARUSER_31_11_1 0xDA2420 #define mmNIC3_QM1_CP_ARUSER_31_11_2 0xDA2424 #define mmNIC3_QM1_CP_ARUSER_31_11_3 0xDA2428 #define mmNIC3_QM1_CP_ARUSER_31_11_4 0xDA242C #define mmNIC3_QM1_CP_AWUSER_31_11_0 0xDA2430 #define mmNIC3_QM1_CP_AWUSER_31_11_1 0xDA2434 #define mmNIC3_QM1_CP_AWUSER_31_11_2 0xDA2438 #define mmNIC3_QM1_CP_AWUSER_31_11_3 0xDA243C #define mmNIC3_QM1_CP_AWUSER_31_11_4 0xDA2440 #define mmNIC3_QM1_ARB_CFG_0 0xDA2A00 #define mmNIC3_QM1_ARB_CHOISE_Q_PUSH 0xDA2A04 #define mmNIC3_QM1_ARB_WRR_WEIGHT_0 0xDA2A08 #define mmNIC3_QM1_ARB_WRR_WEIGHT_1 0xDA2A0C #define mmNIC3_QM1_ARB_WRR_WEIGHT_2 0xDA2A10 #define mmNIC3_QM1_ARB_WRR_WEIGHT_3 0xDA2A14 #define mmNIC3_QM1_ARB_CFG_1 0xDA2A18 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_0 0xDA2A20 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_1 0xDA2A24 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_2 0xDA2A28 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_3 0xDA2A2C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_4 0xDA2A30 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_5 0xDA2A34 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_6 0xDA2A38 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_7 0xDA2A3C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_8 0xDA2A40 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_9 0xDA2A44 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_10 0xDA2A48 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_11 0xDA2A4C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_12 0xDA2A50 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_13 0xDA2A54 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_14 0xDA2A58 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_15 0xDA2A5C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_16 0xDA2A60 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_17 0xDA2A64 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_18 0xDA2A68 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_19 0xDA2A6C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_20 0xDA2A70 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_21 0xDA2A74 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_22 0xDA2A78 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_23 0xDA2A7C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 0xDA2A80 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_25 0xDA2A84 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_26 0xDA2A88 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_27 0xDA2A8C #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_28 0xDA2A90 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_29 0xDA2A94 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_30 0xDA2A98 #define mmNIC3_QM1_ARB_MST_AVAIL_CRED_31 0xDA2A9C #define mmNIC3_QM1_ARB_MST_CRED_INC 0xDA2AA0 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDA2AA4 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDA2AA8 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDA2AAC #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDA2AB0 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDA2AB4 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDA2AB8 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDA2ABC #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDA2AC0 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDA2AC4 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDA2AC8 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDA2ACC #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDA2AD0 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDA2AD4 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDA2AD8 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDA2ADC #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDA2AE0 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDA2AE4 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDA2AE8 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDA2AEC #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDA2AF0 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDA2AF4 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDA2AF8 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDA2AFC #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDA2B00 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDA2B04 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDA2B08 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDA2B0C #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDA2B10 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDA2B14 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDA2B18 #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDA2B1C #define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDA2B20 #define mmNIC3_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDA2B28 #define mmNIC3_QM1_ARB_MST_SLAVE_EN 0xDA2B2C #define mmNIC3_QM1_ARB_MST_QUIET_PER 0xDA2B34 #define mmNIC3_QM1_ARB_SLV_CHOISE_WDT 0xDA2B38 #define mmNIC3_QM1_ARB_SLV_ID 0xDA2B3C #define mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT 0xDA2B44 #define mmNIC3_QM1_ARB_MSG_AWUSER_31_11 0xDA2B48 #define mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDA2B4C #define mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA2B50 #define mmNIC3_QM1_ARB_BASE_LO 0xDA2B54 #define mmNIC3_QM1_ARB_BASE_HI 0xDA2B58 #define mmNIC3_QM1_ARB_STATE_STS 0xDA2B80 #define mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS 0xDA2B84 #define mmNIC3_QM1_ARB_MSG_STS 0xDA2B88 #define mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDA2B8C #define mmNIC3_QM1_ARB_ERR_CAUSE 0xDA2B9C #define mmNIC3_QM1_ARB_ERR_MSG_EN 0xDA2BA0 #define mmNIC3_QM1_ARB_ERR_STS_DRP 0xDA2BA8 #define mmNIC3_QM1_ARB_MST_CRED_STS_0 0xDA2BB0 #define mmNIC3_QM1_ARB_MST_CRED_STS_1 0xDA2BB4 #define mmNIC3_QM1_ARB_MST_CRED_STS_2 0xDA2BB8 #define mmNIC3_QM1_ARB_MST_CRED_STS_3 0xDA2BBC #define mmNIC3_QM1_ARB_MST_CRED_STS_4 0xDA2BC0 #define mmNIC3_QM1_ARB_MST_CRED_STS_5 0xDA2BC4 #define mmNIC3_QM1_ARB_MST_CRED_STS_6 0xDA2BC8 #define mmNIC3_QM1_ARB_MST_CRED_STS_7 0xDA2BCC #define mmNIC3_QM1_ARB_MST_CRED_STS_8 0xDA2BD0 #define mmNIC3_QM1_ARB_MST_CRED_STS_9 0xDA2BD4 #define mmNIC3_QM1_ARB_MST_CRED_STS_10 0xDA2BD8 #define mmNIC3_QM1_ARB_MST_CRED_STS_11 0xDA2BDC #define mmNIC3_QM1_ARB_MST_CRED_STS_12 0xDA2BE0 #define mmNIC3_QM1_ARB_MST_CRED_STS_13 0xDA2BE4 #define mmNIC3_QM1_ARB_MST_CRED_STS_14 0xDA2BE8 #define mmNIC3_QM1_ARB_MST_CRED_STS_15 0xDA2BEC #define mmNIC3_QM1_ARB_MST_CRED_STS_16 0xDA2BF0 #define mmNIC3_QM1_ARB_MST_CRED_STS_17 0xDA2BF4 #define mmNIC3_QM1_ARB_MST_CRED_STS_18 0xDA2BF8 #define mmNIC3_QM1_ARB_MST_CRED_STS_19 0xDA2BFC #define mmNIC3_QM1_ARB_MST_CRED_STS_20 0xDA2C00 #define mmNIC3_QM1_ARB_MST_CRED_STS_21 0xDA2C04 #define mmNIC3_QM1_ARB_MST_CRED_STS_22 0xDA2C08 #define mmNIC3_QM1_ARB_MST_CRED_STS_23 0xDA2C0C #define mmNIC3_QM1_ARB_MST_CRED_STS_24 0xDA2C10 #define mmNIC3_QM1_ARB_MST_CRED_STS_25 0xDA2C14 #define mmNIC3_QM1_ARB_MST_CRED_STS_26 0xDA2C18 #define mmNIC3_QM1_ARB_MST_CRED_STS_27 0xDA2C1C #define mmNIC3_QM1_ARB_MST_CRED_STS_28 0xDA2C20 #define mmNIC3_QM1_ARB_MST_CRED_STS_29 0xDA2C24 #define mmNIC3_QM1_ARB_MST_CRED_STS_30 0xDA2C28 #define mmNIC3_QM1_ARB_MST_CRED_STS_31 0xDA2C2C #define mmNIC3_QM1_CGM_CFG 0xDA2C70 #define mmNIC3_QM1_CGM_STS 0xDA2C74 #define mmNIC3_QM1_CGM_CFG1 0xDA2C78 #define mmNIC3_QM1_LOCAL_RANGE_BASE 0xDA2C80 #define mmNIC3_QM1_LOCAL_RANGE_SIZE 0xDA2C84 #define mmNIC3_QM1_CSMR_STRICT_PRIO_CFG 0xDA2C90 #define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1 0xDA2C94 #define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0 0xDA2C98 #define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1 0xDA2C9C #define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0 0xDA2CA0 #define mmNIC3_QM1_GLBL_AXCACHE 0xDA2CA4 #define mmNIC3_QM1_IND_GW_APB_CFG 0xDA2CB0 #define mmNIC3_QM1_IND_GW_APB_WDATA 0xDA2CB4 #define mmNIC3_QM1_IND_GW_APB_RDATA 0xDA2CB8 #define mmNIC3_QM1_IND_GW_APB_STATUS 0xDA2CBC #define mmNIC3_QM1_GLBL_ERR_ADDR_LO 0xDA2CD0 #define mmNIC3_QM1_GLBL_ERR_ADDR_HI 0xDA2CD4 #define mmNIC3_QM1_GLBL_ERR_WDATA 0xDA2CD8 #define mmNIC3_QM1_GLBL_MEM_INIT_BUSY 0xDA2D00 #endif /* ASIC_REG_NIC3_QM1_REGS_H_ */