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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 | // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_lm.h" #include "dpu_hw_dspp.h" #include "dpu_kms.h" /* DSPP_PCC */ #define PCC_EN BIT(0) #define PCC_DIS 0 #define PCC_RED_R_OFF 0x10 #define PCC_RED_G_OFF 0x1C #define PCC_RED_B_OFF 0x28 #define PCC_GREEN_R_OFF 0x14 #define PCC_GREEN_G_OFF 0x20 #define PCC_GREEN_B_OFF 0x2C #define PCC_BLUE_R_OFF 0x18 #define PCC_BLUE_G_OFF 0x24 #define PCC_BLUE_B_OFF 0x30 static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg) { u32 base = ctx->cap->sblk->pcc.base; if (!ctx || !base) { DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base); return; } if (!cfg) { DRM_DEBUG_DRIVER("disable pcc feature\n"); DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); return; } DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b); DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r); DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g); DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b); DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r); DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g); DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b); DPU_REG_WRITE(&ctx->hw, base, PCC_EN); } static void _setup_dspp_ops(struct dpu_hw_dspp *c, unsigned long features) { if (test_bit(DPU_DSPP_PCC, &features)) c->ops.setup_pcc = dpu_setup_dspp_pcc; } static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, const struct dpu_mdss_cfg *m, void __iomem *addr, struct dpu_hw_blk_reg_map *b) { int i; if (!m || !addr || !b) return ERR_PTR(-EINVAL); for (i = 0; i < m->dspp_count; i++) { if (dspp == m->dspp[i].id) { b->base_off = addr; b->blk_off = m->dspp[i].base; b->length = m->dspp[i].len; b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_DSPP; return &m->dspp[i]; } } return ERR_PTR(-EINVAL); } static struct dpu_hw_blk_ops dpu_hw_ops; struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) { struct dpu_hw_dspp *c; const struct dpu_dspp_cfg *cfg; if (!addr || !m) return ERR_PTR(-EINVAL); c = kzalloc(sizeof(*c), GFP_KERNEL); if (!c) return ERR_PTR(-ENOMEM); cfg = _dspp_offset(idx, m, addr, &c->hw); if (IS_ERR_OR_NULL(cfg)) { kfree(c); return ERR_PTR(-EINVAL); } /* Assign ops */ c->idx = idx; c->cap = cfg; _setup_dspp_ops(c, c->cap->features); dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops); return c; } void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp) { if (dspp) dpu_hw_blk_destroy(&dspp->base); kfree(dspp); } |