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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ %YAML 1.2 --- $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: CPSW Port's Interface Mode Selection PHY Tree Bindings maintainers: - Kishon Vijay Abraham I <kishon@ti.com> description: | TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. The interface mode is selected by configuring the MII mode selection register(s) (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and bit fields placement in SCM are different between SoCs while fields meaning is the same. +--------------+ +-------------------------------+ |SCM | | CPSW | | +---------+ | | +--------------------------------+gmii_sel | | | | | | +---------+ | | +----v---+ +--------+ | +--------------+ | |Port 1..<--+-->GMII/MII<-------> | | | | | | | | +--------+ | +--------+ | | | | | | +--------+ | | | | RMII <-------> | +--> | | | | +--------+ | | | | | | +--------+ | | | | RGMII <-------> | +--> | | | +--------+ | +-------------------------------+ CPSW Port's Interface Mode Selection PHY describes MII interface mode between CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration. | CPSW Port's Interface Mode Selection PHY device should defined as child device of SCM node (scm_conf) and can be attached to each CPSW port node using standard PHY bindings. properties: compatible: enum: - ti,am3352-phy-gmii-sel - ti,dra7xx-phy-gmii-sel - ti,am43xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel reg: maxItems: 1 '#phy-cells': true allOf: - if: properties: compatible: contains: enum: - ti,dra7xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel then: properties: '#phy-cells': const: 1 description: CPSW port number (starting from 1) - if: properties: compatible: contains: enum: - ti,am3352-phy-gmii-sel - ti,am43xx-phy-gmii-sel then: properties: '#phy-cells': const: 2 description: | - CPSW port number (starting from 1) - RMII refclk mode required: - compatible - reg - '#phy-cells' additionalProperties: false examples: - | phy_gmii_sel: phy-gmii-sel@650 { compatible = "ti,am3352-phy-gmii-sel"; reg = <0x650 0x4>; #phy-cells = <2>; }; |