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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 | // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ /dts-v1/; #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/gpio/gpio.h> / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; }; &fpd_dma_chan1 { status = "okay"; }; &fpd_dma_chan2 { status = "okay"; }; &fpd_dma_chan3 { status = "okay"; }; &fpd_dma_chan4 { status = "okay"; }; &fpd_dma_chan5 { status = "okay"; }; &fpd_dma_chan6 { status = "okay"; }; &fpd_dma_chan7 { status = "okay"; }; &fpd_dma_chan8 { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &rtc { status = "okay"; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; }; &uart0 { status = "okay"; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; dr_mode = "host"; }; |