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Defined in 10 files as a macro:
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h, line 59 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h, line 59 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h, line 57 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h, line 63 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h, line 79 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h, line 172 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h, line 352 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h, line 602 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h, line 767 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h, line 1147 (as a macro)