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Defined in 15 files as a macro:
- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c, line 105 (as a macro)
- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c, line 110 (as a macro)
- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c, line 104 (as a macro)
- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c, line 94 (as a macro)
- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c, line 95 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h, line 4609 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h, line 4622 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h, line 5854 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h, line 11670 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h, line 3383 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h, line 3977 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h, line 9953 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h, line 12640 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h, line 12438 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h, line 11295 (as a macro)